Dr. Soumya Pandit

Associate Professor
Institute of Radio Physics and Electronics, University of Calcutta

Conferences

Year Title with page nos. Conference Publications Author / Co-author ISSN/ISBN No API Score
2025/05/13 Statistical Analysis of a Low Power Analog Current Source 2022 IEEE VLSI Device Circuit and System (VLSI DCS) Co-Author ISBN:978-1-6654-3802-5 5
2025/03/05 Machine Learning Algorithm for Handwritten Numerical Character Identification Using FPGA Based Custom IP Core TENCON 2024 - 2024 IEEE Region 10 Conference (TENCON) Co-Author ISBN: 979-8-3503-8010-1979-8-3503-5082-1 5
2025/02/13 A µW Power CMOS Window Detector Circuit with Adjustable Thresholds for Low-Power Applications 2024 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Co-Author ISBN:979-8-3503-7465-0 5
2024/10/09 Design of FPGA based Custom IP Core to Detect the Edges of Brain Tumors 2024 28th International Symposium on VLSI Design and Test (VDAT) Co-Author ISBN: 979-8-3503-8010-1 5
2024/10/09 Design of A Custom IP Core for Concatenated SVM Model to Classify Multi-class Handwritten Numerical Characters 2024 28th International Symposium on VLSI Design and Test (VDAT) Co-Author ISBN: 979-8-3503-8010-1 5
2024/03/20 Hardware Prototyping of Handwritten Character Recognition using VEGA Soft Core Processor 2023 8th International Conference on Computers and Devices for Communication (CODEC) Co-Author ISBN: 979-8-3503-1718-3 5
2023/05/29 A Temperature Compensated Beta-Multiplier Based Sub-1 V Voltage Reference Circuit for Low-Voltage Applications 2023 IEEE Devices for Integrated Circuit (DevIC) Co-Author ISBN: 979-8-3503-4726-5 5
2023/05/29 An approach for modeling propagation delay of a subthreshold inverter incorporating DIBL effect 2023 IEEE Devices for Integrated Circuit (DevIC) Co-Author ISBN: 979-8-3503-4726-5 5
2023/05/01 Reduction of Interconnect Delay and Resistance While Minimizing Grid Area in GNR-Based VLSI Routing Problem International Symposium on Devices, Circuits and Systems (ISDCS), 2022 Co-Author Print ISBN: 978-981-99-0054-1 5
2023/02/09 An Ultra-Low Power (86 nW) Low-Voltage (0.6 V) Self-Biased Instrumentation Amplifier for Bio-Medical Applications 2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Co-Author ISBN: -1-6654-7205-0 5
2022/12/17 Reliability Aware Global Routing of Graphene Nanoribbon Based Interconnect VLSI Design and Test. VDAT 2022 Co-Author Print ISBN: 978-3-031-21513-1 5
2021/06/21 A 0.6 V 1.6 nA Constant Current Reference Circuit with Improved Power Supply Sensitivity 2021 Devices for Integrated Circuit (DevIC) Co-Author ISBN: 978-1-7281-9955-9 5
2021/04/26 Minimization of Switching Activity of Graphene Based Circuits 2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID) Co-author ISBN:978-1-6654-3127-9 5
2020/08/28 Comparative Study of Doublet OTA Circuit Topologies Operating in Weak Inversion Mode for Low Power Analog IC Applications 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Co-Author ISBN: 978-1-7281-1933-5 5
2020/02/20 FPGA Based Hardware Design for Noise Suppression and Seismic Event Detection 2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) Co-Author ISBN: 978-1-7281-4655-3 5
2020/02/13 Crosstalk Aware Global Routing of Graphene Nanoribbon Based Circuits 2019 IEEE 19th International Conference on Nanotechnology (IEEE-NANO) Co-Author ISBN:978-1-7281-2893-1 5
2019/07/15 Temperature Analysis of Threshold Voltage and Sub‐threshold slope of Epitaxial Delta Doped Channel MOS Transistor for SoC Applications Proceedings of 2nd Int. Conf. Microelectronics, Circuits and Systems, organized by IASTM, Editor: D.Acharya Publisher: Arisha Creation, Kolkata Author ISBN: 81‐ 85824‐46‐0 5
2018/06/14 Compact drain current modeling of InAs-OI-Si MOS transistor including quantum confinement 2018 International Symposium on Devices, Circuits and Systems (ISDCS) Co-Author ISBN:978-1-5386-5123-0 5
2017/04/06 Study of analog and RF performance of UTB-OI-Si substrate MOS transistor using buffered InGaAs and Silicon channel 2015 6th International Conference on Computers and Devices for Communication (CODEC) Co-Author ISBN: 978-1-4673-9513-7 5
2017/03/24 Study of LER/LWR Induced VT Variability of an EδDC n‐channel MOS Transistor Devices for Integrated Circuit (DevIC) Author ISBN No: 978‐ 1‐5090‐4724‐6/17 5
2016/03/17 Amino acid classification based on Electrical response of its Codon composition Proceedings of IEEE Int. Conference on Research in Computational Intelligence and Communication Networks Co-Author Electronic ISBN: 978-1- 4673-6735-6 CD-ROM ISBN: 978-1- 4673-6734-9 4
2014/07/18 Study of reverse substrate bias effect of 22nm node epitaxial delta doped channel MOS transistor for low power SoC applications VLSI Design and Test, 18th International Symposium on, Publisher: IEEE Co-Author ISBN: 978-1- 4799-4006-6 5
2014/03/17 Threshold voltage modeling of Deeply Depleted Channel MOSFET and simulation study of its analog performances International Conference on Electronics, Communication and Instrumentation (ICECI) Co-Author Electronic ISBN:978-1-4799-3983-1 5
2011/05/10 Study of Short Channel Characteristics of Gate Underlapped InGaAs‐OI‐Si MOS Transistor Proceedings of NCDC 2016, Editor: A.K.Panda, Publisher: IPM Pvt. Ltd, Odhisha Author ISBN: 978‐93‐ 82208‐78‐5 5
2011/02/20 Statistical Simulation and Modeling of Nano-scale CMOS VCO Using Artificial Neural Network 2011 24th Internatioal Conference on VLSI Design Co-Author ISBN: 978-0-7695-4348-2 5
2009/01/19 Systematic Methodology for High-Level Performance Modeling of Analog Systems 2009 22nd International Conference on VLSI Design Author ISBN: 978-0-7695-3506-7 5
2004/12/30 Study of Wide Temperature Variation (100‐500 K) on Drain Current Characteristics of a 22nm n‐channel EδDC MOS Transistor Proceedings of 4th International. Conference on Computing, Communication and Sensor Network, 2015, organized by IASTM, Editor: D.Acharya, Publisher: IASTM Author ISBN: 81- 85824-46-0 5
2004/04/19 Porous silicon device modeling and linearisation technique 2003 IEEE Conference on Electron Devices and Solid-State Circuits (IEEE Cat. No.03TH8668) Author Print ISBN:0-7803-7749-4 5

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