Dr. Soumya Pandit is an Associate Professor at the Institute of Radio Physics and Electronics, University of Calcutta, India. He received his Ph.D. in VLSI Design from the Indian Institute of Technology Kharagpur, where he worked on high-level synthesis methodologies and CAD tools for CMOS analog circuits. He holds a B.Sc. in Physics (Honours), an M.Sc. in Electronic Science, and an M.Tech. in Radio Physics and Electronics—all from the University of Calcutta.
Dr. Pandit’s research spans over two decades in the fields of ultra-low power analog/mixed-signal circuit design, statistical variability modeling, and compact device modeling. From 2003 to 2008, he served as a Research Consultant at the Advanced VLSI Design Laboratory, IIT Kharagpur, where he led projects sponsored by National Semiconductor (USA) and MeitY, Government of India. His work led to the development of silicon-proven IP and EDA methodologies.
At the University of Calcutta, he has played a key role in developing advanced teaching and research infrastructure. He is the founder and Teacher-in-Charge of the IC Design Laboratory (15 years), a premier facility for postgraduate instruction and research in CMOS Analog ASIC Design. He has also served as Joint Teacher-in-Charge of the Electronic Circuits and Analog Circuits Laboratories (8 years), and the VLSI Design Laboratory (3 years). He has successfully led multiple CMOS tape-outs in 0.8 µm and 0.18 µm nodes.
Dr. Pandit is the Coordinator of both the 2-Year Full-Time M.Tech in VLSI Design (Program Code 102) and the Working Professionals’ M.Tech Program (Program Code 103) at the University of Calcutta, overseeing academic operations, curriculum development, admissions, examinations, and resource management. He has contributed to curriculum reform efforts as a member of the syllabus sub-committees for both B.Tech and M.Tech programs, and has served on the Board of Studies in Electronics and Communication Engineering and VLSI Design for over 13 years.
He has published over 55 papers in reputed international journals and conferences, and is the author of Nano-Scale CMOS Analog Circuits: Models and CAD Techniques for High-Level Design (CRC Press, USA), along with chapters in books from Springer, IET, and CRC Press. He has led research projects funded by DST, UGC, TEQIP, and the University of Calcutta. Currently, he is the Chief Investigator of the MeitY-sponsored "Chips to Startup (C2S)" Program, aimed at developing indigenous semiconductor design capability.
Dr. Pandit has held senior roles in international conferences, including Technical Program Committee (TPC) membership for VLSI Design, VLSI Design and Test, Embedded Computing, ICEE, and OPTRONIX, and served as Ph.D. Forum Chair, Session Chair, and TPC Member across several IEEE and ACM conferences in India.
A Senior Member of IEEE (USA), he is currently the Associate Editor-in-Chief of the IEEE Electron Devices Society (EDS) Newsletter and the founding Chapter Advisor of the IEEE EDS Student Branch Chapter at the University of Calcutta. He previously served as:
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Chair, IEEE EDS Calcutta Chapter (2014–2015)
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Treasurer, IEEE EDS Calcutta Chapter (2012–2013)
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Vice Chair, Student Research Committee, Region 10, IEEE EDS (2018–2021)
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Member, Regions and Chapters Committee, IEEE EDS (2016–2017)
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Regional Editor (Region 10), IEEE EDS Newsletter (2021–2025)
Dr. Pandit also serves as a member of the Board of Studies at the National Institute of Science and Technology, Berhampur, Odisha (BPUT Autonomous). He is a Chartered Engineer (India) and a Fellow of the Institution of Electronics and Telecommunication Engineers (IETE).
His current research focuses on energy-efficient analog/mixed-signal systems, design-aware statistical modeling, and device-circuit co-optimization for next-generation semiconductor technologies.